The NAND flash memory industry is targeting the development of chips with up to 1,000 layers, driven by the demand for higher storage capacity and performance. While the stacking of chips and layers aims to improve bandwidth and reduce latency, this innovation introduces new reliability challenges that manufacturers must address. Pioneers in this space include Toshiba and Samsung, with notable history in stacking techniques like through-silicon vias (TSVs) contributing to advancements. Importantly, export regulations currently restrict the height of NAND stack to 128 layers, which complicates international trade and technology dissemination. There's also a point of contention regarding the ability to create multiple layers in a single lithography step, suggesting a need for clarification among industry experts regarding manufacturing processes.